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499 lines
47 KiB
Markdown
499 lines
47 KiB
Markdown
# cpuid
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Package cpuid provides information about the CPU running the current program.
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CPU features are detected on startup, and kept for fast access through the life of the application.
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Currently x86 / x64 (AMD64/i386) and ARM (ARM64) is supported, and no external C (cgo) code is used, which should make the library very easy to use.
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You can access the CPU information by accessing the shared CPU variable of the cpuid library.
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Package home: https://github.com/klauspost/cpuid
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[](https://pkg.go.dev/github.com/klauspost/cpuid/v2)
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[](https://github.com/klauspost/cpuid/actions/workflows/go.yml)
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## installing
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`go get -u github.com/klauspost/cpuid/v2` using modules.
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Drop `v2` for others.
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Installing binary:
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`go install github.com/klauspost/cpuid/v2/cmd/cpuid@latest`
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Or download binaries from release page: https://github.com/klauspost/cpuid/releases
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### Homebrew
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For macOS/Linux users, you can install via [brew](https://brew.sh/)
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```sh
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$ brew install cpuid
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```
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## example
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```Go
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package main
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import (
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"fmt"
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"strings"
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. "github.com/klauspost/cpuid/v2"
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)
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func main() {
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// Print basic CPU information:
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fmt.Println("Name:", CPU.BrandName)
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fmt.Println("PhysicalCores:", CPU.PhysicalCores)
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fmt.Println("ThreadsPerCore:", CPU.ThreadsPerCore)
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fmt.Println("LogicalCores:", CPU.LogicalCores)
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fmt.Println("Family", CPU.Family, "Model:", CPU.Model, "Vendor ID:", CPU.VendorID)
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fmt.Println("Features:", strings.Join(CPU.FeatureSet(), ","))
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fmt.Println("Cacheline bytes:", CPU.CacheLine)
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fmt.Println("L1 Data Cache:", CPU.Cache.L1D, "bytes")
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fmt.Println("L1 Instruction Cache:", CPU.Cache.L1I, "bytes")
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fmt.Println("L2 Cache:", CPU.Cache.L2, "bytes")
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fmt.Println("L3 Cache:", CPU.Cache.L3, "bytes")
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fmt.Println("Frequency", CPU.Hz, "hz")
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// Test if we have these specific features:
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if CPU.Supports(SSE, SSE2) {
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fmt.Println("We have Streaming SIMD 2 Extensions")
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}
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}
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```
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Sample output:
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```
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>go run main.go
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Name: AMD Ryzen 9 3950X 16-Core Processor
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PhysicalCores: 16
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ThreadsPerCore: 2
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LogicalCores: 32
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Family 23 Model: 113 Vendor ID: AMD
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Features: ADX,AESNI,AVX,AVX2,BMI1,BMI2,CLMUL,CMOV,CX16,F16C,FMA3,HTT,HYPERVISOR,LZCNT,MMX,MMXEXT,NX,POPCNT,RDRAND,RDSEED,RDTSCP,SHA,SSE,SSE2,SSE3,SSE4,SSE42,SSE4A,SSSE3
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Cacheline bytes: 64
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L1 Data Cache: 32768 bytes
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L1 Instruction Cache: 32768 bytes
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L2 Cache: 524288 bytes
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L3 Cache: 16777216 bytes
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Frequency 0 hz
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We have Streaming SIMD 2 Extensions
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```
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# usage
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The `cpuid.CPU` provides access to CPU features. Use `cpuid.CPU.Supports()` to check for CPU features.
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A faster `cpuid.CPU.Has()` is provided which will usually be inlined by the gc compiler.
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To test a larger number of features, they can be combined using `f := CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SYSCALL, SSE, SSE2)`, etc.
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This can be using with `cpuid.CPU.HasAll(f)` to quickly test if all features are supported.
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Note that for some cpu/os combinations some features will not be detected.
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`amd64` has rather good support and should work reliably on all platforms.
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Note that hypervisors may not pass through all CPU features through to the guest OS,
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so even if your host supports a feature it may not be visible on guests.
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## arm64 feature detection
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Not all operating systems provide ARM features directly
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and there is no safe way to do so for the rest.
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Currently `arm64/linux` and `arm64/freebsd` should be quite reliable.
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`arm64/darwin` adds features expected from the M1 processor, but a lot remains undetected.
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A `DetectARM()` can be used if you are able to control your deployment,
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it will detect CPU features, but may crash if the OS doesn't intercept the calls.
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A `-cpu.arm` flag for detecting unsafe ARM features can be added. See below.
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Note that currently only features are detected on ARM,
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no additional information is currently available.
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## flags
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It is possible to add flags that affects cpu detection.
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For this the `Flags()` command is provided.
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This must be called *before* `flag.Parse()` AND after the flags have been parsed `Detect()` must be called.
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This means that any detection used in `init()` functions will not contain these flags.
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Example:
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```Go
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package main
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import (
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"flag"
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"fmt"
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"strings"
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"github.com/klauspost/cpuid/v2"
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)
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func main() {
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cpuid.Flags()
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flag.Parse()
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cpuid.Detect()
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// Test if we have these specific features:
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if cpuid.CPU.Supports(cpuid.SSE, cpuid.SSE2) {
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fmt.Println("We have Streaming SIMD 2 Extensions")
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}
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}
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```
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## commandline
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Download as binary from: https://github.com/klauspost/cpuid/releases
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Install from source:
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`go install github.com/klauspost/cpuid/v2/cmd/cpuid@latest`
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### Example
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```
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λ cpuid
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Name: AMD Ryzen 9 3950X 16-Core Processor
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Vendor String: AuthenticAMD
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Vendor ID: AMD
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PhysicalCores: 16
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Threads Per Core: 2
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Logical Cores: 32
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CPU Family 23 Model: 113
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Features: ADX,AESNI,AVX,AVX2,BMI1,BMI2,CLMUL,CLZERO,CMOV,CMPXCHG8,CPBOOST,CX16,F16C,FMA3,FXSR,FXSROPT,HTT,HYPERVISOR,LAHF,LZCNT,MCAOVERFLOW,MMX,MMXEXT,MOVBE,NX,OSXSAVE,POPCNT,RDRAND,RDSEED,RDTSCP,SCE,SHA,SSE,SSE2,SSE3,SSE4,SSE42,SSE4A,SSSE3,SUCCOR,X87,XSAVE
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Microarchitecture level: 3
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Cacheline bytes: 64
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L1 Instruction Cache: 32768 bytes
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L1 Data Cache: 32768 bytes
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L2 Cache: 524288 bytes
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L3 Cache: 16777216 bytes
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```
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### JSON Output:
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```
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λ cpuid --json
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{
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"BrandName": "AMD Ryzen 9 3950X 16-Core Processor",
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"VendorID": 2,
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"VendorString": "AuthenticAMD",
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"PhysicalCores": 16,
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"ThreadsPerCore": 2,
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"LogicalCores": 32,
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"Family": 23,
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"Model": 113,
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"CacheLine": 64,
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"Hz": 0,
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"BoostFreq": 0,
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"Cache": {
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"L1I": 32768,
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"L1D": 32768,
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"L2": 524288,
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"L3": 16777216
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},
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"SGX": {
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"Available": false,
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"LaunchControl": false,
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"SGX1Supported": false,
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"SGX2Supported": false,
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"MaxEnclaveSizeNot64": 0,
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"MaxEnclaveSize64": 0,
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"EPCSections": null
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},
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"Features": [
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"ADX",
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"AESNI",
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"AVX",
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"AVX2",
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"BMI1",
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"BMI2",
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"CLMUL",
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"CLZERO",
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"CMOV",
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"CMPXCHG8",
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"CPBOOST",
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"CX16",
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"F16C",
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"FMA3",
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"FXSR",
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"FXSROPT",
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"HTT",
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"HYPERVISOR",
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"LAHF",
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"LZCNT",
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"MCAOVERFLOW",
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"MMX",
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"MMXEXT",
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"MOVBE",
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"NX",
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"OSXSAVE",
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"POPCNT",
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"RDRAND",
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"RDSEED",
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"RDTSCP",
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"SCE",
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"SHA",
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"SSE",
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"SSE2",
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"SSE3",
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"SSE4",
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"SSE42",
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"SSE4A",
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"SSSE3",
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"SUCCOR",
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"X87",
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"XSAVE"
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],
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"X64Level": 3
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}
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```
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### Check CPU microarch level
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```
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λ cpuid --check-level=3
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2022/03/18 17:04:40 AMD Ryzen 9 3950X 16-Core Processor
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2022/03/18 17:04:40 Microarchitecture level 3 is supported. Max level is 3.
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Exit Code 0
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λ cpuid --check-level=4
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2022/03/18 17:06:18 AMD Ryzen 9 3950X 16-Core Processor
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2022/03/18 17:06:18 Microarchitecture level 4 not supported. Max level is 3.
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Exit Code 1
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```
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## Available flags
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### x86 & amd64
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| Feature Flag | Description |
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|--------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
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| ADX | Intel ADX (Multi-Precision Add-Carry Instruction Extensions) |
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| AESNI | Advanced Encryption Standard New Instructions |
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| AMD3DNOW | AMD 3DNOW |
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| AMD3DNOWEXT | AMD 3DNowExt |
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| AMXBF16 | Tile computational operations on BFLOAT16 numbers |
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| AMXINT8 | Tile computational operations on 8-bit integers |
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| AMXFP16 | Tile computational operations on FP16 numbers |
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| AMXTILE | Tile architecture |
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| APX_F | Intel APX |
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| AVX | AVX functions |
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| AVX10 | If set the Intel AVX10 Converged Vector ISA is supported |
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| AVX10_128 | If set indicates that AVX10 128-bit vector support is present |
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| AVX10_256 | If set indicates that AVX10 256-bit vector support is present |
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| AVX10_512 | If set indicates that AVX10 512-bit vector support is present |
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| AVX2 | AVX2 functions |
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| AVX512BF16 | AVX-512 BFLOAT16 Instructions |
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| AVX512BITALG | AVX-512 Bit Algorithms |
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| AVX512BW | AVX-512 Byte and Word Instructions |
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| AVX512CD | AVX-512 Conflict Detection Instructions |
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| AVX512DQ | AVX-512 Doubleword and Quadword Instructions |
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| AVX512ER | AVX-512 Exponential and Reciprocal Instructions |
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| AVX512F | AVX-512 Foundation |
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| AVX512FP16 | AVX-512 FP16 Instructions |
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| AVX512IFMA | AVX-512 Integer Fused Multiply-Add Instructions |
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| AVX512PF | AVX-512 Prefetch Instructions |
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| AVX512VBMI | AVX-512 Vector Bit Manipulation Instructions |
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| AVX512VBMI2 | AVX-512 Vector Bit Manipulation Instructions, Version 2 |
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| AVX512VL | AVX-512 Vector Length Extensions |
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| AVX512VNNI | AVX-512 Vector Neural Network Instructions |
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| AVX512VP2INTERSECT | AVX-512 Intersect for D/Q |
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| AVX512VPOPCNTDQ | AVX-512 Vector Population Count Doubleword and Quadword |
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| AVXIFMA | AVX-IFMA instructions |
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| AVXNECONVERT | AVX-NE-CONVERT instructions |
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| AVXSLOW | Indicates the CPU performs 2 128 bit operations instead of one |
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| AVXVNNI | AVX (VEX encoded) VNNI neural network instructions |
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| AVXVNNIINT8 | AVX-VNNI-INT8 instructions |
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| AVXVNNIINT16 | AVX-VNNI-INT16 instructions |
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| BHI_CTRL | Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598 |
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| BMI1 | Bit Manipulation Instruction Set 1 |
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| BMI2 | Bit Manipulation Instruction Set 2 |
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| CETIBT | Intel CET Indirect Branch Tracking |
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| CETSS | Intel CET Shadow Stack |
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| CLDEMOTE | Cache Line Demote |
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| CLMUL | Carry-less Multiplication |
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| CLZERO | CLZERO instruction supported |
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| CMOV | i686 CMOV |
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| CMPCCXADD | CMPCCXADD instructions |
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| CMPSB_SCADBS_SHORT | Fast short CMPSB and SCASB |
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| CMPXCHG8 | CMPXCHG8 instruction |
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| CPBOOST | Core Performance Boost |
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| CPPC | AMD: Collaborative Processor Performance Control |
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| CX16 | CMPXCHG16B Instruction |
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| EFER_LMSLE_UNS | AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ |
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| ENQCMD | Enqueue Command |
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| ERMS | Enhanced REP MOVSB/STOSB |
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| F16C | Half-precision floating-point conversion |
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| FLUSH_L1D | Flush L1D cache |
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| FMA3 | Intel FMA 3. Does not imply AVX. |
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| FMA4 | Bulldozer FMA4 functions |
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| FP128 | AMD: When set, the internal FP/SIMD execution datapath is 128-bits wide |
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| FP256 | AMD: When set, the internal FP/SIMD execution datapath is 256-bits wide |
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| FSRM | Fast Short Rep Mov |
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| FXSR | FXSAVE, FXRESTOR instructions, CR4 bit 9 |
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| FXSROPT | FXSAVE/FXRSTOR optimizations |
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| GFNI | Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage. |
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| HLE | Hardware Lock Elision |
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| HRESET | If set CPU supports history reset and the IA32_HRESET_ENABLE MSR |
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| HTT | Hyperthreading (enabled) |
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| HWA | Hardware assert supported. Indicates support for MSRC001_10 |
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| HYBRID_CPU | This part has CPUs of more than one type. |
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| HYPERVISOR | This bit has been reserved by Intel & AMD for use by hypervisors |
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| IA32_ARCH_CAP | IA32_ARCH_CAPABILITIES MSR (Intel) |
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| IA32_CORE_CAP | IA32_CORE_CAPABILITIES MSR |
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| IBPB | Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB) |
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| IBRS | AMD: Indirect Branch Restricted Speculation |
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| IBRS_PREFERRED | AMD: IBRS is preferred over software solution |
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| IBRS_PROVIDES_SMP | AMD: IBRS provides Same Mode Protection |
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| IBS | Instruction Based Sampling (AMD) |
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| IBSBRNTRGT | Instruction Based Sampling Feature (AMD) |
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| IBSFETCHSAM | Instruction Based Sampling Feature (AMD) |
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| IBSFFV | Instruction Based Sampling Feature (AMD) |
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| IBSOPCNT | Instruction Based Sampling Feature (AMD) |
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| IBSOPCNTEXT | Instruction Based Sampling Feature (AMD) |
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| IBSOPSAM | Instruction Based Sampling Feature (AMD) |
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| IBSRDWROPCNT | Instruction Based Sampling Feature (AMD) |
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| IBSRIPINVALIDCHK | Instruction Based Sampling Feature (AMD) |
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| IBS_FETCH_CTLX | AMD: IBS fetch control extended MSR supported |
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| IBS_OPDATA4 | AMD: IBS op data 4 MSR supported |
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| IBS_OPFUSE | AMD: Indicates support for IbsOpFuse |
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| IBS_PREVENTHOST | Disallowing IBS use by the host supported |
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| IBS_ZEN4 | Fetch and Op IBS support IBS extensions added with Zen4 |
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| IDPRED_CTRL | IPRED_DIS |
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| INT_WBINVD | WBINVD/WBNOINVD are interruptible. |
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| INVLPGB | NVLPGB and TLBSYNC instruction supported |
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| KEYLOCKER | Key locker |
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| KEYLOCKERW | Key locker wide |
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| LAHF | LAHF/SAHF in long mode |
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| LAM | If set, CPU supports Linear Address Masking |
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| LBRVIRT | LBR virtualization |
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| LZCNT | LZCNT instruction |
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| MCAOVERFLOW | MCA overflow recovery support. |
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| MCDT_NO | Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it. |
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| MCOMMIT | MCOMMIT instruction supported |
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| MD_CLEAR | VERW clears CPU buffers |
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| MMX | standard MMX |
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| MMXEXT | SSE integer functions or AMD MMX ext |
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| MOVBE | MOVBE instruction (big-endian) |
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| MOVDIR64B | Move 64 Bytes as Direct Store |
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| MOVDIRI | Move Doubleword as Direct Store |
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| MOVSB_ZL | Fast Zero-Length MOVSB |
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| MPX | Intel MPX (Memory Protection Extensions) |
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| MOVU | MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD |
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| MSRIRC | Instruction Retired Counter MSR available |
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| MSRLIST | Read/Write List of Model Specific Registers |
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| MSR_PAGEFLUSH | Page Flush MSR available |
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| NRIPS | Indicates support for NRIP save on VMEXIT |
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| NX | NX (No-Execute) bit |
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| OSXSAVE | XSAVE enabled by OS |
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| PCONFIG | PCONFIG for Intel Multi-Key Total Memory Encryption |
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| POPCNT | POPCNT instruction |
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| PPIN | AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled |
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| PREFETCHI | PREFETCHIT0/1 instructions |
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| PSFD | Predictive Store Forward Disable |
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| RDPRU | RDPRU instruction supported |
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| RDRAND | RDRAND instruction is available |
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| RDSEED | RDSEED instruction is available |
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| RDTSCP | RDTSCP Instruction |
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| RRSBA_CTRL | Restricted RSB Alternate |
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| RTM | Restricted Transactional Memory |
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| RTM_ALWAYS_ABORT | Indicates that the loaded microcode is forcing RTM abort. |
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| SERIALIZE | Serialize Instruction Execution |
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| SEV | AMD Secure Encrypted Virtualization supported |
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| SEV_64BIT | AMD SEV guest execution only allowed from a 64-bit host |
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| SEV_ALTERNATIVE | AMD SEV Alternate Injection supported |
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| SEV_DEBUGSWAP | Full debug state swap supported for SEV-ES guests |
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| SEV_ES | AMD SEV Encrypted State supported |
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| SEV_RESTRICTED | AMD SEV Restricted Injection supported |
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| SEV_SNP | AMD SEV Secure Nested Paging supported |
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| SGX | Software Guard Extensions |
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| SGXLC | Software Guard Extensions Launch Control |
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| SHA | Intel SHA Extensions |
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| SME | AMD Secure Memory Encryption supported |
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| SME_COHERENT | AMD Hardware cache coherency across encryption domains enforced |
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| SPEC_CTRL_SSBD | Speculative Store Bypass Disable |
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| SRBDS_CTRL | SRBDS mitigation MSR available |
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| SSE | SSE functions |
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| SSE2 | P4 SSE functions |
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| SSE3 | Prescott SSE3 functions |
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| SSE4 | Penryn SSE4.1 functions |
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| SSE42 | Nehalem SSE4.2 functions |
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| SSE4A | AMD Barcelona microarchitecture SSE4a instructions |
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| SSSE3 | Conroe SSSE3 functions |
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| STIBP | Single Thread Indirect Branch Predictors |
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| STIBP_ALWAYSON | AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On |
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| STOSB_SHORT | Fast short STOSB |
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| SUCCOR | Software uncorrectable error containment and recovery capability. |
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| SVM | AMD Secure Virtual Machine |
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| SVMDA | Indicates support for the SVM decode assists. |
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| SVMFBASID | SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control |
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| SVML | AMD SVM lock. Indicates support for SVM-Lock. |
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| SVMNP | AMD SVM nested paging |
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| SVMPF | SVM pause intercept filter. Indicates support for the pause intercept filter |
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| SVMPFT | SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold |
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| SYSCALL | System-Call Extension (SCE): SYSCALL and SYSRET instructions. |
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| SYSEE | SYSENTER and SYSEXIT instructions |
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| TBM | AMD Trailing Bit Manipulation |
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| TDX_GUEST | Intel Trust Domain Extensions Guest |
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| TLB_FLUSH_NESTED | AMD: Flushing includes all the nested translations for guest translations |
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| TME | Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. |
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| TOPEXT | TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX. |
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| TSCRATEMSR | MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104 |
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| TSXLDTRK | Intel TSX Suspend Load Address Tracking |
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| VAES | Vector AES. AVX(512) versions requires additional checks. |
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| VMCBCLEAN | VMCB clean bits. Indicates support for VMCB clean bits. |
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| VMPL | AMD VM Permission Levels supported |
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| VMSA_REGPROT | AMD VMSA Register Protection supported |
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| VMX | Virtual Machine Extensions |
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| VPCLMULQDQ | Carry-Less Multiplication Quadword. Requires AVX for 3 register versions. |
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| VTE | AMD Virtual Transparent Encryption supported |
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| WAITPKG | TPAUSE, UMONITOR, UMWAIT |
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| WBNOINVD | Write Back and Do Not Invalidate Cache |
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| WRMSRNS | Non-Serializing Write to Model Specific Register |
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| X87 | FPU |
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| XGETBV1 | Supports XGETBV with ECX = 1 |
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| XOP | Bulldozer XOP functions |
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| XSAVE | XSAVE, XRESTOR, XSETBV, XGETBV |
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| XSAVEC | Supports XSAVEC and the compacted form of XRSTOR. |
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| XSAVEOPT | XSAVEOPT available |
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| XSAVES | Supports XSAVES/XRSTORS and IA32_XSS |
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# ARM features:
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| Feature Flag | Description |
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|--------------|------------------------------------------------------------------|
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| AESARM | AES instructions |
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| ARMCPUID | Some CPU ID registers readable at user-level |
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| ASIMD | Advanced SIMD |
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| ASIMDDP | SIMD Dot Product |
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| ASIMDHP | Advanced SIMD half-precision floating point |
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| ASIMDRDM | Rounding Double Multiply Accumulate/Subtract (SQRDMLAH/SQRDMLSH) |
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| ATOMICS | Large System Extensions (LSE) |
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| CRC32 | CRC32/CRC32C instructions |
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| DCPOP | Data cache clean to Point of Persistence (DC CVAP) |
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| EVTSTRM | Generic timer |
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| FCMA | Floatin point complex number addition and multiplication |
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| FP | Single-precision and double-precision floating point |
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| FPHP | Half-precision floating point |
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| GPA | Generic Pointer Authentication |
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| JSCVT | Javascript-style double->int convert (FJCVTZS) |
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| LRCPC | Weaker release consistency (LDAPR, etc) |
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| PMULL | Polynomial Multiply instructions (PMULL/PMULL2) |
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| SHA1 | SHA-1 instructions (SHA1C, etc) |
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| SHA2 | SHA-2 instructions (SHA256H, etc) |
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| SHA3 | SHA-3 instructions (EOR3, RAXI, XAR, BCAX) |
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| SHA512 | SHA512 instructions |
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| SM3 | SM3 instructions |
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| SM4 | SM4 instructions |
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| SVE | Scalable Vector Extension |
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# license
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This code is published under an MIT license. See LICENSE file for more information.
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